1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly to an array substrate having an improved aperture ratio and brightness and a method of fabricating the array substrate.
2. Discussion of the Related Art
Since a liquid crystal display (LCD) device has characteristics of light weight, thinness and low power consumption, LCD devices have been widely used, particularly in televisions, computer monitors, cellular phone displays, personal digital assistants (PDAs) and etc. Among the known types of LCD devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images.
Generally, the LCD device is manufactured through an array substrate fabricating process, a color filter substrate fabricating process and a cell process. In the array substrate fabricating process, array elements, such as a TFT and a pixel electrode, are formed on a first substrate. In the color filter substrate fabricating process, a color filter and a common electrode are formed on a second substrate. In a cell process, the first and second substrates are attached to each other with a liquid crystal interposed therebetween.
FIG. 1 is an exploded perspective view of a related art LCD device. The LCD device includes first and second substrates 12 and 22, and a liquid crystal layer 30. The first and second substrates 12 and 22 face each other, and the liquid crystal layer 30 is interposed therebetween.
The first substrate 12 includes a gate line 14, a data line 16, a TFT “Tr”, and a pixel electrode 18. The first substrate 12 including these elements is referred to as an array substrate 10. The gate line 14 and the data line 16 cross each other such that a region is formed between the gate and data lines 14 and 16 and is defined as a pixel region “P”. The TFT “Tr” is formed at a crossing portion between the gate and data lines 14 and 16, and the pixel electrode 18 is formed in the pixel region “P” and connected to the TFT “Tr”.
The second substrate 22 includes a black matrix 25, a color filter layer 26, and a common electrode 28. The second substrate 22 including these elements is referred to as a color filter substrate 20. The black matrix 25 has a lattice shape to cover a non-display region of the first substrate 12, such as the gate line 14, the data line 16, the TFT “Tr”. The color filter layer 26 includes first, second, and third sub-color filters 26a, 26b, and 26c. Each of the sub-color filters 26a, 26b, and 26c has one of red, green, and blue colors R, G, and B and corresponds to the each pixel region “P”. The common electrode 28 is formed on the black matrix 25 and the color filter layers 26 and over an entire surface of the second substrate 22.
Although not shown, to prevent the liquid crystal layer 30 from leaking, a seal pattern may be formed along edges of the first and second substrates 12 and 22. First and second alignment layers may be formed between the first substrate 12 and the liquid crystal layer 30 and between the second substrate 22 and the liquid crystal layer 30. A polarizer may be formed on an outer surface of the first and second substrates 12 and 22.
An LCD device includes a backlight assembly opposing an outer surface of the first substrate 12 to supply light to the liquid crystal layer 30. When a scanning signal is applied to the gate line 14 to control the TFT “Tr”, a data signal is applied to the pixel electrode 18 through the data line 16 such that the electric field is induced between the pixel and common electrodes 18 and 28. Then, the electric field causes the liquid crystals to switch on and as a result, the LCD device produces images using the light from the backlight assembly.
FIG. 2 is a cross-sectional view of one pixel region of an array substrate for a related art LCD device. A gate line and a data line 79 are formed on a substrate 59. The gate line and the data line 79 cross each other to define a pixel region P. A gate electrode 63 connected to the gate line is formed at a switching region TrA in the pixel region P. A gate insulating layer 66 is formed on the gate line and the gate electrode 63. A semiconductor layer 76 including an active layer 67 and an ohmic contact layer 74 is formed on the gate insulating layer to correspond to the gate electrode 63. A source electrode 82 and a drain electrode 84 are formed on the ohmic contact layer 74. The source electrode 82 is connected to the data line 79, and the drain electrode 84 is spaced apart from the source electrode 82. The gate electrode 63, the gate insulating layer 66, the semiconductor layer 76, the source electrode 82 and the drain electrode 84 constitute a TFT Tr in the switching region TrA. A passivation layer 86 including a drain contact hole 87 is formed on the data line and the TFT Tr. The drain contact hole 87 exposes a portion of the drain electrode 84. A pixel electrode 88 is formed on the passivation layer 86 in each pixel region P and contacts the drain electrode 84 through the drain contact hole 87.
The semiconductor layer 76 protrudes beyond the source and drain electrodes with a first width “A1” above about 2 micrometers. In addition, a semiconductor pattern 73 including a first pattern 72 and a second pattern 68 protrudes beyond the data line 79 with a second width “A2” above about 2 micrometers at each side. It is because the array substrate 59 is formed by a four mask process. The four mask process is explained with reference to accompanied drawings.
FIGS. 3A to 3H are cross-sectional views showing a four mask process for fabricating an array substrate according to the related art.
In FIG. 3A, a first metallic material layer is formed on the substrate 59. The first metallic material layer is patterned by a first mask process to form the gate line and the gate electrode 63. The gate electrode 63 is disposed in the switching region TrA. Although not shown, the first mask process includes a step of forming a photoresist (PR) layer, a step of exposing the PR layer to light using a first mask, a step of developing the exposed PR layer to form a PR pattern, a step of etching the first metallic material layer using the PR pattern as an etching mask to form the gate line and the gate electrode 63 and a step of stripping the PR pattern.
In FIG. 3B, a gate insulating layer 66, an intrinsic amorphous silicon layer 69, an impurity-doped amorphous silicon layer 70 and a second metallic material layer 78 are sequentially formed on the gate line and the gate electrode 63. A PR layer is formed on the second metallic material layer 78 and patterned using a second mask to form first and second PR patterns 91a and 91b. The second mask may be a refractive exposing mask or a half-tone exposing mask. The first PR pattern 91a has a first thickness and corresponds to the source electrode, the drain electrode and the data line. The second PR pattern 91b has a second thickness smaller than the first thickness and corresponds to a center of the gate electrode 63. Namely, the second PR pattern 91b corresponds to a space between the source and drain electrodes. The PR layer in other portions is completely removed such that the second metallic material layer 78 is exposed.
In FIG. 3C, the exposed second metal material layer 78 (of FIG. 3B) is wet-etched with an etchant using the first and second PR patterns 91a and 91b as an etching mask to form the data line 79 and a metallic material pattern 80. The impurity-doped amorphous silicon layer 70 is exposed between the data line 79 and the metallic material pattern 80. The second metallic material layer 78 (of FIG. 3B) may include a low resistance metallic material. For example, the second metallic material layer 78 (of FIG. 3B) may include one of copper (Cu), Cu alloy, aluminum (Al), Al alloy. When the second metallic material layer 78 (of FIG. 3B) includes Cu or Cu alloy, the second metallic material layer 78 (of FIG. 3B) has a relatively high etching rate for the etchant. Accordingly, the data line 79 and the metallic material pattern 80 have an undercut structure under the first PR pattern 91a. Namely, the data line 79 has a width smaller than the first PR pattern 91a, and a width of the metallic material pattern 80 is smaller than that of the first and second PR patterns 91a and 91b in the switching region TrA.
In FIG. 3D, the exposed impurity-doped amorphous silicon layer 70 (of FIG. 3C) and the intrinsic amorphous silicon layer 69 (of FIG. 3C) are dry-etched using the first and second PR patterns 91a and 91b to form an ohmic contact pattern 71 and an active layer 67 under the metallic material pattern 80. At the same time, a first pattern 72 of impurity-doped amorphous silicon and a second pattern 68 of intrinsic amorphous silicon are formed under the data line 79. The first pattern 72 and the second pattern 68 constitute a semiconductor pattern 73. Since the ohmic contact pattern 71 and the active layer 67 are formed using the first and second PR patterns 91a and 91b as an etching mask, they have a width greater than the metallic material pattern 80.
In FIG. 3E, an ashing process is performed onto the substrate 59. As a result, the second PR pattern 91b is removed such that a portion of the metallic material pattern 80 is exposed. A thickness of the first PR pattern 91a is reduced such that a third PR pattern 92 is formed. The third PR pattern 92 may have the same width as the first PR pattern 91a. In this case, outer ends of the third PR pattern 92 on the metallic material pattern 80 may be overlap ends of the ohmic contact pattern 71, and outer ends of the third PR pattern 92 on the data line 79 may be overlap ends of the first pattern 72. On the other hand, the third PR pattern 92 may have a width smaller than the first PR pattern 91a because of the ashing process. In this case, outer ends of the third PR patterns 92 on the metallic material pattern 80 and the data line 79 are disposed within the ohmic contact pattern 71 and the first pattern 72, respectively.
In FIG. 3F, the portion of the metallic material pattern 80 (of FIG. 3E) exposed by removing the second PR pattern 91b (of FIG. 3E) is wet-etched using an etchant to form the source electrode 82 and the drain electrode 84. As a result, the source electrode 82 and the drain electrode 84 are disposed on the ohmic contact pattern 71 and spaced apart from each other. Since the metallic material pattern 80 (of FIG. 3E) has a relatively high etching rate for the etchant, the source electrode 82, the drain electrode 84 and the data line 79 experience a significant undercut effect with the third PR pattern 92.
In FIG. 3G, the portion of the ohmic contact pattern 71 exposed between the source and drain electrodes 82 and 84 is dry-etched to form an ohmic contact layer 74 under the source and drain electrodes 82 and 84. At the same time, a portion of the active layer 67 is exposed through the ohmic contact layer 74 to define a channel. The gate electrode 63, the gate insulating layer 66, a semiconductor layer 76 including the active layer 67 and the ohmic contact layer 74, the source electrode 82 and the drain electrode 84 constitute the TFT Tr in the switching region TrA.
In FIG. 3H, the third PR pattern 92 (of FIG. 3G) is stripped. Then, the passivation layer 86 including the drain contact hole 87 is formed on the data line 79 and the TFT Tr by a third mask process. The drain contact hole 87 exposes a portion of the drain electrode 84. The pixel electrode 88 contacting the drain electrode 84 through the drain contact hole 87 is formed on the passivation layer 86 by a fourth mask process. The array substrate is fabricated by the above four mask processes.
As mentioned above, in the related array substrate, the semiconductor pattern 73 including the first pattern 72 and the second pattern 68 under the data line 79 protrudes beyond the data line 79 with a range above about 2 micrometers at each side. Since the pixel electrode 88 is disposed to be spaced apart with a predetermined distance from the semiconductor pattern 73, aperture ratio is reduced due to the distance between the data line 79 and the pixel electrode 88. Therefore, it is desired to reduce the distance between the data line 79 and the pixel electrode 88 in order to improve the aperture ratio.